Metal oxide semiconductor field effect transistors (MOSFET) have gained a great deal of acceptance in power applications. The basic principal of the MOSFET is as follows. A source and a drain region of silicon have a first conductivity type, and a region of opposite conductivity type silicon is disposed there between. A gate metalization or polysilicon is disposed on top of the middle region of the semiconductor, with a layer of oxide disposed between the gate and the semiconductor. Current does not flow between the source and the drain under an unbiased condition, due to the potential barrier formed by the interfaces of the semiconductors. Conduction is made possible when the surface region of the channel underneath the oxide layer is inverted by the electric field resulting from an applied gate bias voltage.
Changes in the fundamental lateral structure of the device were necessitated before the MOSFET structure could compete with the current-handling capabilities of a bipolar transistor structure. The planar MOSFET proved unsuitable for power operation for a variety of reasons. A successful development of a power MOSFET was achieved with the adoption of vertical current flow through the silicon. By placing the source and drain on opposite sides of the silicon wafer, the depletion region is spread out through the silicon vertically rather than laterally thereby allowing a greater concentration of FET cells on the surface, resulting in a more efficient use of available space to enable power applications to be realized. The vertical structure metal oxide semiconductor transistors in which current flow is vertical are commonly known as VDMOS. The VDMOS structure is a double diffused structure wherein a groove is etched into the structure after successive diffusions have established the appropriate vertical diffusion profile in the silicon. A gate oxide is grown on the surface of the groove and a metal gate deposited there after on the oxide. The channel length is determined by the difference in the depths of the p and n diffusion. The VDMOS structure is an enhancement mode device which requires only a single bias polarity. Frequency limits in such a device is a function of the gate length and the saturation velocity. High frequency VDMOS structures utilize self-aligned polysilicon gates and implant/diffusion profiles to control the gate length. Finally, the VDMOS structure has a drain contact on the bottom of the die and of late has proved to have frequency response values up to a 1.0 GHz. Further understanding of the basic concepts of metal oxide structures and devices can be found in Power MOSFETs: Power for the 80s by Grant, et al., Solid State Technology, November 1985, the disclosure of which is specifically incorporated herein by reference.
Another structure which is being used in power MOS applications is the lateral double diffused metal oxide semiconductor FET (LDMOS FET). In the LDMOS structure, the source and drain contacts are both on the same surface of the wafer as is the gate. Accordingly, an interdigitated electrode structure is used. That is, the source, drain and gate repeat in large scale integration. The rate of repetition in spacial dimensions is known as the pitch of the device; for example the distance from the source of a first device to the source of the next device. In the device in which the substrate is nominally p-type, the subject of the disclosure of the present invention, the source is connected to the substrate, which is at ground. The LDMOS structure has a number of significant advantages when compared to the VDMOS structure. One such advantage is that the LDMOS structure enables device isolation so that multiple LDMOS devices can be fabricated on the same substrate for an integrated amplifier design, for example. The LDMOS structure has a number of significant reductions in parasitic capacitance by virtue of its structure, which translate into a comparably higher frequency response over a vertical structure. To this end, the gate-to-source capacitance C.sub.gs as well as the drain-to-source capacitance, C.sub.ds have inherently lower values when compare to the VDMOS structure. LDMOS devices have certain other advantages when compared to VDMOS structures. First of all, as alluded to above, LDMOS structures have the potential applicability in VLSI and LSI. In contrast, vertical structures such as VDMOS can not be readily fabricated in large scale. This is by virtue of the vertical nature of the device which does not lend itself to on wafer fabrication in large scale. In addition, the vertical structures have attendant practical drawback, because the source in a comparable vertical structure MOS device is not grounded, and the LDMOS source is grounded, the vertical structure device must be isolated and cannot be mounted on a common ground metalization or plane as can be done in the lateral devices. Typical isolation is done with ceramics to include beryllium oxide, which increase greatly the packaging costs of the device increase stray capacitance and have a poor ability to dissipate joule heat. In contrast, the LDMOS device can be grounded directly to a common metalization eliminating the need for the isolating ceramic, which thereby reduces the cost. Stray capacitances are not added in this structure, and the thermal dissipation of metal is clearly an advantage in power applications. Accordingly, across the industry there is an increasing trend to explore the applicability of LDMOS structures in high frequency power applications.
As stated previously, the source is connected to ground in the structure in which the substrate is p-type. This is done conventionally via a wire bond connection from the source contact to the back side metalization of the device. Such a structure, while accomplishing the required connection, has a significant drawback in the introduction of an undesired parasitic inductance. In addition to introducing an undesired inductance, particularly at higher frequencies, the wire bonding technique of the conventional design requires a greater labor input, resulting in a significant component in the overall cost of the device.
The device structure shown in FIG. 1 is this typical lateral device having the p.sup.++ sinker. This sinker is shown at 101. The sinker overcomes the necessity to effect a wire bond between the source metalization and ground on the reverse side of the die. Typically the sinker 101 is effected through a very high doping concentration of boron. Creating a conductive path from the top of the device to the bottom of the device at the device level. In addition to effecting this contact without the need for a wire bond, the sinker at the device level has the advantage of providing a relatively low resistance path. Source resistance to ground must be maintained at a very low level in order to achieve a higher gain. The conventional technique of using a highly concentrated sinker at the device level to achieve low ground resistance does accomplish certain advantages as stated over a wire bonding. Unfortunately, this structure has certain disadvantages. One major disadvantage of this technique of implanting a highly doped sinker, is that by the very nature of the doping process, as well as the desire to have a low resistance path, a large area is consumed. By using up valuable real estate the pitch of the device is increased. That is, as is well known to one of ordinary skill in the art, across a given amplifier, the inter-digitation of device elements is used to densely populate across a wafer. This large scale integration technique often has a source/gate/drain/gate/source, etc. sequence. The distance from the far edge of the first gate of one device and the near edge of a second gate of a second device, is known as the pitch. In order to densely populate a wafer, the pitch should be reduced as much as possible to enable more devices per unit area of the wafer. More devices per unit area of real estate translates into more power in amplifier applications. The sinker of the conventional boron doped connection between the source metalization and the substrate has an unacceptable pitch for large scale power applications. Furthermore, while the super doping to effect the sinker does provide for a somewhat acceptable source resistance, this clearly could be improved as well.
Accordingly, what is needed is a device which enables the common source configuration of a LDMOS structure which reduces the source resistance while at the same time decreases the pitch of the device.